The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2018

Filed:

Aug. 09, 2013
Applicant:

Chuo University, Hachioji-shi, Tokyo, JP;

Inventors:

Tomoko Iwasaki, Tokyo, JP;

Kosuke Miyaji, Tokyo, JP;

Ken Takeuchi, Tokyo, JP;

Assignee:

CHUO UNIVERSITY, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 11/56 (2006.01); G11C 29/06 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0009 (2013.01); G11C 13/0002 (2013.01); G11C 13/004 (2013.01); G11C 13/0033 (2013.01); G11C 13/0064 (2013.01); G11C 13/0069 (2013.01); G11C 11/56 (2013.01); G11C 13/0004 (2013.01); G11C 29/06 (2013.01); G11C 2013/0047 (2013.01); G11C 2013/0057 (2013.01); G11C 2013/0073 (2013.01); G11C 2013/0092 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.


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