Data sense amplification circuit and semiconductor memory device including the same

Abstract

A semiconductor memory device includes: a first memory cell coupled to a first bit line; a second memory cell coupled to a second bit line; and a sense amplification circuit for sensing and amplifying a voltage difference between the first and second bit lines, wherein the sense amplification circuit includes: a first sense amplifier including a cross-coupled pair of first and second transistors coupled to the first bit line and the second bit line, respectively; a second sense amplifier including a cross-coupled pair of third and fourth transistors coupled to the first and second bit lines, respectively; and an offset supplier for controlling a timing for supplying a voltage of the first bit line to the first transistor and a timing for supplying a voltage of the second bit line to the second transistor according to a selected memory from the first and second memory cells.