The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Nov. 22, 2013
Applicant:
Nvidia Corporation, Santa Clara, CA (US);
Inventors:
Michael Asbury Woodmansee, Lighthouse Point, FL (US);
J. Arjun Prabhu, Palo Alto, CA (US);
Assignee:
NVIDIA Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0895 (2016.01); G06F 11/16 (2006.01); G11C 29/00 (2006.01); G06F 11/20 (2006.01); G11C 29/04 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0895 (2013.01); G06F 11/16 (2013.01); G06F 11/1666 (2013.01); G11C 29/76 (2013.01); G06F 11/20 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/4402 (2013.01); Y10T 29/41 (2015.01);
Abstract
An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit.