The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2018
Filed:
Dec. 08, 2015
Sandisk Technologies Inc., Plano, TX (US);
Prasad Naidu, Bangalore, IN;
Jayanth Mysore Thimmaiah, Bangalore, IN;
Prashant Singhai, Bangalore, IN;
SanDisk Technologies LLC, Plano, TX (US);
Abstract
A high output voltage Vlevel and a low output voltage Vlevel parametric test system may include test circuitry coupled to output nodes of input/output (I/O) driver circuits. The test circuitry may source and sink current to the output nodes while the I/O driver circuits are in pull down and pull up states, respectively, in order to generate output voltages on the output nodes. The parametric test system may compare the output voltages with a plurality of high and low reference levels to determine ranges of the output voltages. The ranges may be used to determine whether the I/O driver circuits pass the Vand Vtest requirements. The V/Vtest system may be implemented on-chip with other components of the external device, which may eliminate the need to perform other parametric testing with external test equipment.