The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Apr. 04, 2014
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Ivan Hugh McLean, Solana Beach, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); H04L 9/32 (2006.01); H04L 9/30 (2006.01); G01R 31/317 (2006.01); G06F 21/33 (2013.01);
U.S. Cl.
CPC ...
H04L 9/3263 (2013.01); G01R 31/31705 (2013.01); G01R 31/31719 (2013.01); G06F 21/335 (2013.01); H04L 9/30 (2013.01); H04L 63/0807 (2013.01);
Abstract

A disabled debug capability may be securely re-enabled in an integrated circuit such as a system-on-a-chip (SoC) device. In a method, the integrated circuit receives a debug re-enable message. The debug re-enable message includes a debug re-enable token signed by a private key. The debug re-enable token is based on a serial number of the integrated circuit and a first copy of a symmetric key. The debug re-enable token is validated using a public key corresponding to the private key. A comparison token is generated using the serial number of the integrated circuit and using a second copy of the symmetric key stored in a one-time-programmable (OTP) memory of the integrated circuit. The integrated circuit compares the debug re-enable token and the comparison token. The disabled debug capability is re-enabled in the integrated circuit if the debug re-enable token matches the comparison token.


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