The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

May. 09, 2017
Applicant:

Beken Corporation, Shanghai, CN;

Inventors:

Dawei Guo, Shanghai, CN;

Caogang Yu, Shanghai, CN;

Assignee:

BEKEN CORPORATION, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/133 (2014.01); H03L 7/08 (2006.01); H03C 3/09 (2006.01); H03L 7/197 (2006.01); H03D 3/24 (2006.01); H03K 21/00 (2006.01); G11B 7/09 (2006.01); G06F 7/499 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0805 (2013.01); G06F 7/49942 (2013.01); G11B 7/0943 (2013.01); H03C 3/0908 (2013.01); H03D 3/241 (2013.01); H03D 3/248 (2013.01); H03K 5/133 (2013.01); H03K 21/00 (2013.01); H03L 7/1976 (2013.01);
Abstract

A circuit for compensating quantized noise in fractional-N frequency synthesizer, comprising a PLL circuit that locks a phase compensated signal to a phase of a reference phase, wherein the phase lock loop circuit comprises a frequency divider and a phase frequency detector; a sigma-delta modulation and phase difference calculator coupled to the frequency divider generating an accumulated phase error by accumulating all previous differences between an input of the frequency divider and an output of the frequency divider within a period; a digital controlled delay line coupled to both the frequency divider and the SDM and Phase Difference calculator and generates the phase compensated signal by multiplying the accumulated phase error with a delay control word; and the phase frequency detector further generates a phase error by comparing the phase compensated signal with the reference clock.


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