The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Nov. 16, 2016
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Austin H. Lesea, Los Gatos, CA (US);

Stephen M. Trimberger, Incline Village, NV (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03K 19/003 (2006.01); H01L 23/00 (2006.01); H01L 23/525 (2006.01); H03K 19/177 (2006.01); G05F 1/46 (2006.01); G06F 21/86 (2013.01);
U.S. Cl.
CPC ...
H03K 19/003 (2013.01); G05F 1/46 (2013.01); G06F 21/86 (2013.01); H01L 23/5256 (2013.01); H01L 23/576 (2013.01); H03K 19/17744 (2013.01); H03K 19/17768 (2013.01);
Abstract

A system includes an integrated circuit (IC) chip with connections to plurality of external pins. An integrated voltage regulator circuit is configured to provide an internal supply voltage to the IC chip. Isolation circuitry is configured to inhibit tampering of the internal supply voltage through the external pins. An analog to digital converter (ADC) circuit is configured to monitor parameters of the internal supply voltage. Security circuitry is configured to detect, using the monitored parameters, indications of tampering and to generate an error signal in response to detecting an indication of tampering.


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