The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jan. 27, 2017
Applicant:

Infineon Technologies Dresden Gmbh, Dresden, DE;

Inventors:

Rolf Weis, Dresden, DE;

Martin Bartels, Dresden, DE;

Marko Lemke, Dresden, DE;

Stefan Tegen, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/45 (2013.01); H01L 21/28518 (2013.01); H01L 29/0696 (2013.01); H01L 29/1095 (2013.01); H01L 29/66696 (2013.01); H01L 29/7825 (2013.01);
Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.


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