The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Apr. 15, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;

Inventors:

Chanwoo Yang, Siheung-si, KR;

Do-Hyun Kim, Seongnam-si, KR;

Jeongju Park, Seoul, KR;

Junhyun Park, Suwon-si, KR;

Doohyoung Lee, Suwon-si, KR;

Xinxing Li, Suwon-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 21/467 (2006.01); H01L 29/66 (2006.01); H01L 21/4757 (2006.01); H01L 29/417 (2006.01); H01L 29/45 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 21/467 (2013.01); H01L 21/47573 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1259 (2013.01); H01L 29/41733 (2013.01); H01L 29/45 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); H01L 29/78606 (2013.01); H01L 27/124 (2013.01);
Abstract

A thin film transistor include a control electrode, a semiconductor layer on the control electrode, an input electrode, at least a portion of the input electrode being on the semiconductor layer, and an output electrode spaced apart from the input electrode, at least a portion of the output electrode being on the semiconductor layer. Each of the input electrode and the output electrode includes a wiring layer including a metal material, a dummy portion on a side part of the wiring layer, the dummy portion including an oxide of the metal material, and a protection layer on the wiring layer, the protection layer overlapping the wiring layer and the dummy portion.


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