The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jun. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Josephine B. Chang, Mahopac, NY (US);

Paul Chang, Mahopac, NY (US);

Michael A. Guillorn, Yorktown Heights, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/768 (2006.01); H01L 21/8234 (2006.01); H01L 23/535 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/76837 (2013.01); H01L 21/76897 (2013.01); H01L 21/823418 (2013.01); H01L 21/823475 (2013.01); H01L 23/535 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/665 (2013.01); H01L 29/401 (2013.01);
Abstract

A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.


Find Patent Forward Citations

Loading…