The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

May. 29, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Gerhard Schmidt, Wernberg, AT;

Markus Kahn, Rangersdorf, AT;

Christian Maier, Egg am See, AT;

Philipp Koch, Villach, AT;

Juergen Steinbrenner, Noetsch, AT;

Assignee:

INFINEON TECHNOLOGIES AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/06 (2006.01); H01L 29/16 (2006.01); H01L 21/3065 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02115 (2013.01); H01L 21/02164 (2013.01); H01L 21/02301 (2013.01); H01L 21/02315 (2013.01); H01L 21/28194 (2013.01); H01L 29/0615 (2013.01); H01L 29/0619 (2013.01); H01L 29/1602 (2013.01); H01L 29/1604 (2013.01); H01L 29/51 (2013.01); H01L 21/02046 (2013.01); H01L 21/3065 (2013.01); H01L 29/66181 (2013.01);
Abstract

According to various embodiments, a method for processing a semiconductor layer may include: generating an etch plasma in a plasma chamber of a remote plasma source, wherein the plasma chamber of the remote plasma source is coupled to a processing chamber for processing the semiconductor layer; introducing the etch plasma into the processing chamber to remove a native oxide layer from a surface of the semiconductor layer and at most a negligible amount of semiconductor material of the semiconductor layer; and, subsequently, depositing a dielectric layer directly on the surface of the semiconductor layer.


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