The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Mar. 15, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Chulmin Jung, San Diego, CA (US);

Po-Hung Chen, San Diego, CA (US);

David Li, San Diego, CA (US);

Sei Seung Yoon, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 8/08 (2006.01); G11C 8/10 (2006.01); G11C 8/06 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 8/08 (2013.01); G11C 8/06 (2013.01); G11C 8/10 (2013.01); G11C 5/14 (2013.01);
Abstract

A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a plurality of word lines. Each word line is driven through a decoder level-shifter that processes the decoded signals. Each decoder level-shifter corresponds to a unique combination of the decoded signals. The row decoder is in a logic power domain such that the decoded signals are asserted to a logic power supply voltage. When a decoder level-shifter's unique combination of decoded signals are asserted by the row decoder, the decoder level-shifter drives the corresponding word line with a memory power supply voltage for a memory power domain.


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