The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Nov. 24, 2014
Applicant:

Sanmina Corporation, San Jose, CA (US);

Inventors:

Sharad Mehrotra, Saratoga, CA (US);

Jon Livesey, Sunnyvale, CA (US);

Thomas Gourley, Banks, OR (US);

Abbas Morshed, Los Altos, CA (US);

Assignee:

Sanmina Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0866 (2016.01); G06F 3/06 (2006.01); H04L 29/08 (2006.01); G06F 12/0811 (2016.01); H04L 29/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0866 (2013.01); G06F 3/067 (2013.01); G06F 3/0613 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 12/08 (2013.01); G06F 12/0811 (2013.01); H04L 67/1097 (2013.01); H04L 67/38 (2013.01); G06F 2211/1009 (2013.01);
Abstract

A system is provided comprising: a packet routing network; Flash storage circuitry; a management processor coupled as an endpoint to the network; an input/output (I/O) circuit coupled as an endpoint to the network; a packet processing circuit coupled as an endpoint to the network; a cache storage circuit coupled to send and received packets to and from the packet processing circuit; and a RAID management circuit coupled as an endpoint to the network and configured to send and receive packets to and from the Flash storage circuitry; wherein the management processor is configured to determine routing of packets among the I/O circuit, packet processing circuit and RAID management circuit; and wherein the packet processing circuit is configured to control cache read requests, cache write requests and cache data eviction.


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