The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Oct. 07, 2016
Applicant:

Silicon Motion, Inc., Jhubei, Hsinchu County, TW;

Inventors:

Chien-Cheng Lin, Yilan, TW;

Jie-Hao Lee, Kaohsiung, TW;

Assignee:

SILICON MOTION, INC., Jhubei, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/16 (2006.01); G11C 7/04 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/064 (2013.01); G06F 3/0616 (2013.01); G06F 3/0679 (2013.01); G11C 7/04 (2013.01); G11C 11/5628 (2013.01); G11C 11/5635 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/3495 (2013.01); G11C 29/70 (2013.01); G06F 2212/202 (2013.01); G06F 2212/214 (2013.01); G06F 2212/222 (2013.01); G11C 2211/5641 (2013.01);
Abstract

The present invention provides a data storage device including a flash memory and a controller. The controller distributes TLC-data blocks of the flash memory into three regions, obtains three sub-prewrite data sectors according to a prewrite data sector and a logic address, determines a first TLC-data block according to the logic address, selects a new first TLC-data block with the lowest erase count from the first region when the first TLC-data block has valid data, selects two TLC-data blocks according to the new first TLC-data block, writes the three sub-prewrite data sectors into the new first TLC-data block and the two selected TLC-data blocks, and maps the first new TLC-data block and the two selected TLC-data blocks to the logic address.


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