The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Sep. 23, 2014
Applicant:

Hgst Netherlands B.v., Amsterdam, NL;

Inventors:

Krishanth Skandakumaran, Los Gatos, CA (US);

Arun Kumar Medapati, Andhra Pradesh, IN;

Sri Rama Namala, San Jose, CA (US);

Ashwin Narasimha, Sunnyvale, CA (US);

Ajith Kumar B, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 13/20 (2006.01); G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); G06F 3/06 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0613 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0688 (2013.01); G06F 13/4221 (2013.01); Y02B 60/1228 (2013.01); Y02B 60/1235 (2013.01);
Abstract

Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.


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