The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Dec. 27, 2012
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Madhu Swarna, Portland, OR (US);

Tezaswi Raja, San Jose, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/3228 (2013.01); Y02B 60/1285 (2013.01); Y02B 60/32 (2013.01);
Abstract

One embodiment provides a method for reducing leakage current in device logic having an operational supply-voltage threshold, a nonzero data-retention supply-voltage threshold, and two or more on-die transistor switches to switchably connect a voltage source to the device logic. After the logic enters an idle period, one or more of the switches are opened to lower a supply voltage of the logic below the operational supply-voltage threshold but above the data-retention supply-voltage threshold. When the logic exits the idle period, one or more of the switches are closed to raise the supply voltage of the logic above the operational supply-voltage threshold.


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