The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2018

Filed:

Jun. 21, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Todor Georgiev Georgiev, Sunnyvale, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04N 7/18 (2006.01); H04N 5/225 (2006.01); G02B 7/00 (2006.01); G02B 21/00 (2006.01); G06T 7/00 (2017.01); G01M 11/00 (2006.01); G02B 13/00 (2006.01); G02B 27/10 (2006.01); G02B 27/14 (2006.01); G02B 27/62 (2006.01); G02B 21/36 (2006.01); G02B 27/60 (2006.01);
U.S. Cl.
CPC ...
G02B 7/003 (2013.01); G01M 11/00 (2013.01); G02B 13/0085 (2013.01); G02B 21/0016 (2013.01); G02B 21/365 (2013.01); G02B 27/1073 (2013.01); G02B 27/144 (2013.01); G02B 27/60 (2013.01); G02B 27/62 (2013.01); G06T 7/0004 (2013.01); G06T 7/004 (2013.01); G06T 7/0024 (2013.01); H04N 5/2254 (2013.01); G06T 2207/30148 (2013.01);
Abstract

Certain aspects relate to systems and techniques for submicron alignment in wafer optics. One disclosed method of alignment between wafers to produce an integrated lens stack employs a beam splitter (that is, a 50% transparent mirror) that reflects the alignment mark of the top wafer when the microscope objective is focused on the alignment mark of the bottom wafer. Another disclosed method of alignment between wafers to produce an integrated lens stack implements complementary patterns that can produce a Moiré effect when misaligned in order to aid in visually determining proper alignment between the wafers. In some embodiments, the methods can be combined to increase precision.


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