The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Mar. 07, 2016
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Willem Zwart, Edinburgh, GB;

John Bruce Bowlerwell, Peterhead, GB;

Michael Page, Stonehouse, GB;

Alastair Boomer, Edinburgh, GB;

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/40 (2006.01); H04L 5/14 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
H04L 12/40013 (2013.01); G06F 13/4291 (2013.01); H04L 5/1476 (2013.01); G06F 13/4027 (2013.01); G06F 13/4282 (2013.01); G06F 2213/0016 (2013.01);
Abstract

A method of sending information between first and second modules connected by a signal bus comprises generating a clock signal in the first module, and imposing the clock signal on a first line of the bus. A first pattern of bit values is transmitted from the second module to the first module on a second line of the bus, during first half-periods of each period of said clock signal. A second pattern of bit values is transmitted from the first module to the second module on the second line of the bus, during second half-periods of each period of said clock signal, wherein the second half-periods of each period of said clock signal are different from the first half-periods of each period of said clock signal. Information can then be transmitted from the first module to the second module by altering the second pattern of bit values; and information can be transmitted from the second module to the first module by altering the first pattern of bit values.


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