The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Jul. 19, 2016
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventor:

Robert Michael Bunce, Cary, NC (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/08 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0037 (2013.01); H03L 7/0807 (2013.01); H04L 1/0042 (2013.01); H04L 7/0012 (2013.01);
Abstract

An apparatus for setting the timing of a triggering edge of a clock signal with respect to received parallel data. The apparatus includes a set of flip-flops including respective data inputs, respective clock inputs, and respective data outputs, wherein the set of flip-flops are configured to generate a set of output data at the data output based on parallel data applied to the respective data inputs in response to a triggering edge of a clock signal applied to the clock inputs; a variable delay element configured to apply a calibrated delay to the clock signal; and a controller configured to generate a control signal for the variable delay element to apply the calibrated delay to the clock signal based on the set of output data generated at the data outputs of the set of flip-flops.


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