The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Dec. 11, 2015
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventor:

Naoshi Ishikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/15 (2006.01);
U.S. Cl.
CPC ...
H03K 5/1506 (2013.01);
Abstract

The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves. A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.


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