The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Nov. 04, 2015
Applicant:

Toshiba Memory Corporation, Minato-ku, Tokyo, JP;

Inventors:

Gen Toyota, Oita Oita, JP;

Shouta Inoue, Oita Oita, JP;

Susumu Yamamoto, Oita Oita, JP;

Takamasa Tanaka, Oita Oita, JP;

Takamitsu Yoshida, Oita Oita, JP;

Kazumasa Tanida, Oita Oita, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/18 (2006.01); H01L 21/304 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 31/18 (2013.01); H01L 21/304 (2013.01); H01L 21/6835 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01);
Abstract

According to one embodiment, a method of manufacturing a semiconductor device includes a step of grinding to thin a first semiconductor wafer on which a semiconductor device is formed in a state in which a surface of a second semiconductor wafer is fixed on a chuck table of a grinding device after bonding the first semiconductor wafer to the second semiconductor wafer. The method includes a step of fixing a surface of the first semiconductor wafer on the chuck table and grinding the surface of the second semiconductor wafer in a state in which the first semiconductor wafer is bonded to the second semiconductor wafer prior to the grinding step to thin the first semiconductor wafer.


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