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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9935194 B1

PDFFull Text
Date of Patent:
Apr. 03, 2018

Filed:

Dec. 06, 2016

3d semiconductor integrated circuit device and method of manufacturing the same

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Jin Ha Kim, Gyeonggi-do, KR;

Jun Kwan Kim, Gyeonggi-do, KR;

Kang Sik Choi, Gyeonggi-do, KR;

Su Jin Chae, Gyeonggi-do, KR;

Young Ho Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Kimberly Rizallah

Assistant Examiner:

Brian Turner

Int. Cl.
CPC ...
H01L 29/94 (2006.01); H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 27/24 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); H01L 21/28518 (2013.01); H01L 21/28531 (2013.01); H01L 27/2454 (2013.01); H01L 29/456 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01);
Abstract

A 3D semiconductor integrated circuit device and a method of manufacturing the same are provided. An active pillar is formed on a semiconductor substrate, and an interlayer insulating layer is formed so that the active pillar is buried in the interlayer insulating layer. The interlayer insulating layer is etched to form a hole so that the active pillar and a peripheral region of the active pillar are exposed. An etching process is performed on the peripheral region of the active pillar exposed through the hole by a certain depth, and a space having the depth is provided between the active pillar and the interlayer insulating layer. A silicon material layer is formed to be buried in the space having the depth, and an ohmic contact layer is formed on the silicon material layer and the active pillar.

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