The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Aug. 21, 2015
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;

Inventors:

Mang Zhao, Wuhan, CN;

Gui Chen, Wuhan, CN;

Yong Tian, Wuhan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01); H03K 5/135 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1222 (2013.01); H01L 27/092 (2013.01); H01L 27/124 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 29/41733 (2013.01); H01L 29/78603 (2013.01); H01L 29/78606 (2013.01); H01L 29/78633 (2013.01); H01L 29/78648 (2013.01); H01L 29/78675 (2013.01); H03K 5/135 (2013.01);
Abstract

A control circuit of a thin film transistor, comprising: a substrate; a silicon nitride layer disposed on the substrate; a silicon dioxide layer disposed on the silicon nitride layer; a light shielding layer disposed inside the silicon nitride layer, which comprising a first light shielding region and a second light shielding region; at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region; each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer synchronized with a second control signal received by the light shielding layer in voltage variation.


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