The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9934862 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 03, 2018

Filed:

Feb. 03, 2017
Applicant:

Empire Technology Development Llc, Wilmington, DE;

Inventors:

Yanjun Ma, Bellevue, WA (US);

Edwin Kan, Ithaca, NY (US);

Assignee:

EMPIRE TECHNOLOGY DEVELOPMENT LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/26 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/54 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 16/24 (2006.01); G11C 16/32 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/08 (2013.01); G11C 7/1006 (2013.01); G11C 11/54 (2013.01); G11C 11/56 (2013.01); G11C 11/5621 (2013.01); G11C 11/5642 (2013.01); G11C 11/5678 (2013.01); G11C 13/004 (2013.01); G11C 13/0004 (2013.01); G11C 13/0061 (2013.01); G11C 16/0408 (2013.01); G11C 16/24 (2013.01); G11C 16/32 (2013.01); G11C 16/0483 (2013.01); G11C 2211/5648 (2013.01);
Abstract

Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an architecture may be implemented to rank memory cells such as volatile memories, non-volatile memories, and other types of data storage devices, where there may not be an equivalent to threshold voltage. In other examples, an arbitrary group of circuits, such as in neural networks where there may not be an equivalent control gate to set the timing resolution, may be ranked. Relative sense timing may be used to rank the cells having different current carrying abilities. A ramped gate voltage may be used to control the timing resolution and to reduce contention between close separate cells. Digital logic may be used to latch and/or record the rank information.


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