The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Aug. 24, 2017
Applicant:

Headway Technologies, Inc., Milpitas, CA (US);

Inventors:

Yaguang Wei, Pleasanton, CA (US);

Yuhui Tang, Milpitas, CA (US);

Moris Dovek, San Jose, CA (US);

Yue Liu, Fremont, CA (US);

Assignee:

Headway Technologies, Inc., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/127 (2006.01); G11B 5/31 (2006.01); G11B 5/147 (2006.01);
U.S. Cl.
CPC ...
G11B 5/315 (2013.01); G11B 5/1278 (2013.01); G11B 5/1475 (2013.01); G11B 5/3116 (2013.01);
Abstract

A PMR writer is disclosed wherein magnetic flux return from a magnetic medium to a main pole is substantially greater through a trailing shield structure than through a leading return loop comprised of a leading shield, return path layer (RTP), and back gap connection (BGC). Magnetic impedance is increased between the RTP and main pole in the leading return loop by removing one or more layers in the BGC and replacing with dielectric material and non-magnetic metal to form a dielectric gap between the RTP and main pole. The non-magnetic metal may be Cu that is electrically isolated from coils within the write head. As a result, area density control and bit error rate are improved over a conventional dual write shield (DWS) structure comprising two flux return pathways. Moreover, adjacent track erasure is maintained at a level similar to a DWS design.


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