The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Jul. 22, 2016
Applicant:

Bitmicro Llc, Reston, VA (US);

Inventors:

Cyrill C. Ponce, Malabon, PH;

Marizonne Operio Fuentes, Leyte, PH;

Gianico Geonzon Noble, Laguna, PH;

Assignee:

BiTMICRO LLC, Reston, VA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 12/1081 (2016.01); G11C 7/10 (2006.01); G06F 13/28 (2006.01); G06F 13/16 (2006.01); G06F 12/0875 (2016.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1081 (2013.01); G06F 12/0875 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G11C 7/1072 (2013.01); G06F 3/061 (2013.01); G06F 3/0683 (2013.01); G06F 2212/452 (2013.01);
Abstract

The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are started simultaneously instead of serially and get instructions from the descriptors provided and set-up by the processor. Each source and destination core's descriptorsare correlated or tied with each other by the processor by providing information to the hardware assist mechanism. The hardware assist mechanism responsible for moderating the data transfer from source to destination. The flow tracker guarantees that data needed by destination exists. By applying the invention to the prior approach/solution, the data latency between the flash & IO bus will be reduced. Processor interrupts will be minimized while data transfer between the flash & IO bus is ongoing.


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