The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Sep. 28, 2016
Applicant:

Marvell International Ltd., Hamilton, BM;

Inventors:

Viney Gautam, San Jose, CA (US);

Yicheng Guo, Milpitas, CA (US);

Hunglin Hsu, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/10 (2016.01); G06F 12/0864 (2016.01); G06F 12/0895 (2016.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0864 (2013.01); G06F 12/0895 (2013.01); G06F 12/1063 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/152 (2013.01);
Abstract

A circuit has an address generation circuit to produce a virtual address (VA) and an index signal and a multi-way cache circuit. The cache circuit has a plurality of Random Access Memory (RAM) groups and a hash function circuit to generate a hash output from the VA. Each RAM group includes RAMs respectively corresponding to the ways. The cache circuit selects, using the hash output, a selected RAM group of the RAM groups, and performs, using the index signal as an address, an operation using one or more RAMs of the selected RAM group. Controlling a multi-way cache circuit comprises determining a hash value using a VA, selecting, using the hash value, a RAM group from a plurality of RAM groups, and performing an operation by using one or more RAMs of the selected RAM group. The RAMs of each RAM group respectively correspond to the ways.


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