The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Feb. 06, 2017
Applicants:

Kuo-tseng Tseng, San Jose, CA (US);

Parkson Wong, Los Altos, CA (US);

Inventors:

Kuo-Tseng Tseng, San Jose, CA (US);

Parkson Wong, Los Altos, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/487 (2006.01); G06F 7/483 (2006.01); G06F 7/53 (2006.01); G06F 7/48 (2006.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
G06F 7/4876 (2013.01); G06F 7/4824 (2013.01); G06F 7/4833 (2013.01); G06F 7/5306 (2013.01); H03K 19/20 (2013.01);
Abstract

In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.


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