The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Mar. 01, 2016
Applicant:

Futurewei Technologies, Inc., Plano, TX (US);

Inventors:

Zongrong Liu, Pleasanton, CA (US);

Qianfan Xu, San Jose, CA (US);

Rongsheng Miao, San Jose, CA (US);

Hongmin Chen, Davis, CA (US);

Xiao Shen, San Bruno, CA (US);

Yu Sheng Bai, Los Altos Hills, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/36 (2006.01); G02B 6/136 (2006.01); G02B 6/132 (2006.01); G02B 6/30 (2006.01); G02B 6/12 (2006.01);
U.S. Cl.
CPC ...
G02B 6/136 (2013.01); G02B 6/132 (2013.01); G02B 6/30 (2013.01); G02B 6/3652 (2013.01); G02B 2006/121 (2013.01);
Abstract

A method for fabricating a photonic integrated circuit (PIC) comprises providing a wafer comprising an insulator layer positioned between a top semiconductor layer and a base semiconductor layer, patterning the top semiconductor layer to simultaneously define a waveguide and a first etch mask window for forming a fiber-guiding v-groove that substantially aligns to an axis of optical signal propagation of the waveguide, removing a first portion of the top semiconductor layer to form the waveguide according to the patterning, removing a second portion of the top semiconductor layer to form the first etch mask window according to the patterning, and forming the fiber-guiding v-groove according to the first etch mask window.


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