The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2018

Filed:

Nov. 28, 2013
Applicant:

Telefonaktiebolaget Lm Ericsson (Publ), Stockholm, SE;

Inventors:

Göran Selander, Bromma, SE;

Mats Näslund, Bromma, SE;

Elena Dubrova, Sollentuna, SE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 11/00 (2006.01); G01R 31/317 (2006.01); G01R 31/3181 (2006.01); G11C 19/28 (2006.01); G01R 31/3185 (2006.01); G11C 29/02 (2006.01); G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31703 (2013.01); G01R 31/3177 (2013.01); G01R 31/31723 (2013.01); G01R 31/31813 (2013.01); G01R 31/318547 (2013.01); G11C 19/28 (2013.01); G11C 29/02 (2013.01); G11C 29/021 (2013.01);
Abstract

A Feedback Shift-Register (FSR) enabling improved testing, e.g., Built-In Self-Tests (BIST), is provided. Each cell of the FSR may either be an observable cell, associated with a non-trivial feedback function implemented by a combinational logic circuit, or a controllable cell, having an associated state variable which belongs to the dependence set of exactly one of the non-trivial feedback functions. Each controllable cell is provided with a multiplexer for selecting either a predecessor cell of the controllable cell or a test value as input. Thus, the sequential circuit of the FSR in an embodiment is tested using tests for combinational logic. The disclosed test procedures utilize a minimal set of test vectors and allow detection of all single stuck-at faults in the FSR. The resulting dynamic power dissipation during test can be considerably less than known BIST designs.


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