The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Mar. 11, 2015
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventor:

Seth Spiel, San Francisco, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01); H03K 17/74 (2006.01); G06F 1/26 (2006.01);
U.S. Cl.
CPC ...
H03K 17/687 (2013.01); G06F 1/263 (2013.01); H03K 17/74 (2013.01);
Abstract

An apparatus includes a first power supply switch, a second power supply switch, and a control circuit. The first power supply switch includes a P-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) having a drain coupled to a first power rail to receive a first power voltage, a source coupled to an output node, and a gate to selectively turn on or off the PMOSFET to supply the first power voltage to the output node or isolate the first power rail. The second power supply switch receives a second power voltage and passes it to the output node if the second power voltage is present. The control circuit cooperates with the first power supply switch to control the gate voltage to turn on the PMOSFET if the first power voltage is present and the second power voltage is absent, and turn off the PMOSFET if the second power voltage is present.


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