The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

May. 13, 2016
Applicants:

Bo-young Seo, Suwon-si, KR;

Yong-seok Chung, Seoul, KR;

Gwan-hyeob Koh, Seoul, KR;

Yong-kyu Lee, Gwacheon-si, KR;

Inventors:

Bo-young Seo, Suwon-si, KR;

Yong-seok Chung, Seoul, KR;

Gwan-hyeob Koh, Seoul, KR;

Yong-kyu Lee, Gwacheon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01L 43/08 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1675 (2013.01); G11C 11/161 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1673 (2013.01); H01L 27/228 (2013.01); H01L 43/08 (2013.01);
Abstract

A resistive memory apparatus includes a memory cell array having a plurality of memory cells and a first ground switch. The plurality of memory cells are arranged in a plurality of rows and a plurality of columns, and each memory cell in a first column of the plurality of memory cells is connected between a first bitline and a first source line. The first ground switch is connected in parallel with the first source line, and the first ground switch is configured to selectively provide a first current path from the first bitline to ground through a selected memory cell in the first column of the plurality of memory cells and the first source line, the current path traversing only a portion of the first source line.


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