The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2018
Filed:
Nov. 19, 2015
Applicant:
Altera Corporation, San Jose, CA (US);
Inventor:
John Curtis Van Dyken, Caledon East, CA;
Assignee:
Altera Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/17 (2006.01); H03K 19/177 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/505 (2013.01); G06F 17/5068 (2013.01); H03K 19/1774 (2013.01); H03K 19/17728 (2013.01); H03K 19/17736 (2013.01); H03K 19/17744 (2013.01); H03K 19/17752 (2013.01); H03K 19/17756 (2013.01);
Abstract
Systems and methods for time-multiplexed synchronous logic provide an enhanced time delay multiplexing (TDM) scheme that includes soft TDM logic generated by computer-aided design (CAD) tools to actualize a circuit design with improved density. The CAD tools can be used to utilize inherent regularity to devise time multiplexing user logic. The CAD can generate soft TDM hardware to realize a circuit design with improved density.