The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Jun. 11, 2015
Applicants:

Dae-kwon Kang, Yongin-si, KR;

Ji-young Jung, Hwaseong-si, KR;

Dong-gyun Kim, Seoul, KR;

Jae-seok Yang, Hwaseong-si, KR;

Sung-wook Hwang, Gyeongsangbuk-do, KR;

Inventors:

Dae-Kwon Kang, Yongin-si, KR;

Ji-young Jung, Hwaseong-si, KR;

Dong-Gyun Kim, Seoul, KR;

Jae-Seok Yang, Hwaseong-si, KR;

Sung-Wook Hwang, Gyeongsangbuk-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Gyeonggi-Do,, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); G06F 17/50 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5068 (2013.01); G06F 17/5081 (2013.01); H01L 21/0274 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01);
Abstract

In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.


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