The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Aug. 14, 2017
Applicant:

Microsemi Solutions (U.s.), Inc., Aliso Viejo, CA (US);

Inventor:

Theodore Wilson, Vancouver, CA;

Assignee:

Microsemi Solutions (U.S.), Inc., Aliso Viejo, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 17/505 (2013.01); G06F 2217/62 (2013.01); G06F 2217/78 (2013.01); G06F 2217/84 (2013.01);
Abstract

An apparatus for monitoring operation of a design under test (DUT) includes an incoming clock edge input; an outgoing clock edge input; an enable input; a protocol input; an upstream clocking input; and a downstream clocking input. The apparatus also includes a memory in communication with the inputs for storing values from the inputs, and a processor in communication with the memory and the inputs, the processor programmed to determine spurious and missing active clock edges sent from the monitored clock gate. The apparatus also includes a clock categorization output to output the determination of the active clock edges from the monitored clock gate as missing or spurious.


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