The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2018

Filed:

Dec. 04, 2015
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andrew David Tune, Sheffield, GB;

Peter Andrew Riocreux, Sheffield, GB;

Sean James Salisbury, Sheffield, GB;

Daniel Adam Sara, Sheffield, GB;

George Robert Scott Lloyd, Sheffield, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/36 (2006.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01); G06F 13/364 (2006.01); G06F 12/0815 (2016.01); G06F 13/40 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 12/0815 (2013.01); G06F 13/404 (2013.01); G06F 13/4282 (2013.01); G06F 2212/621 (2013.01);
Abstract

An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard management circuitry is used to serialize transactions to overlapping addresses. In addition, gating circuitry ensures ordered write observation (OWO) behavior at an interface to one or more of the master devices, the gating circuitry receiving write address transfers of write transactions and performing a gating operation to gate onward propagation of the write address transfers to the slave devices in order to ensure the OWO behavior. The gating circuitry performs the gating operation under control of the hazard management circuitry. Hence, for write transactions that are subjected to hazard checking by the hazard management circuitry, this removes the need to implement any other processes to specifically manage OWO behavior for those write transactions.


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