The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Sep. 18, 2015
Applicant:

Taiyo Yuden Co., Ltd., Tokyo, JP;

Inventors:

Masayuki Satou, Tokyo, JP;

Isao Shimizu, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); G11C 7/00 (2006.01); G11C 11/00 (2006.01); G06F 9/50 (2006.01); G11C 8/10 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); H04N 19/00 (2014.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); G06F 9/5061 (2013.01); G11C 7/00 (2013.01); G11C 8/10 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H03K 19/1776 (2013.01); H03K 19/17736 (2013.01); H03K 19/17744 (2013.01); H04N 19/00 (2013.01);
Abstract

Main memory access from a CPU is reduced, and thus an increase in speed of data processing is achieved. Provided is a reconfigurable device () connected to a main memory (). The reconfigurable device () includes a plurality of logic sections connected to each other by an address line or a data line. Each of the logic sections includes a plurality of address lines, a plurality of data lines, an address decoder that decodes addresses input from part of the plurality of address lines, and a memory cell array unit that includes a plurality of memory cells specified by decode lines of the address decoder, and outputs data read from the specified memory cells to the data lines. An address line of the memory cell array unit is connected to a data output line (RD) of the main memory.


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