The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Mar. 10, 2017
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventors:
Hiroyoshi Kudou, Ibaraki, JP;
Taro Moriya, Ibaraki, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7813 (2013.01); H01L 29/0619 (2013.01); H01L 29/0634 (2013.01); H01L 29/66734 (2013.01);
Abstract
An n-channel power MOS transistor having a gate electrode is formed in an element formation region defined in a semiconductor substrate. A p-type guard ring region is formed in a terminal region. A plurality of p-type column regions are formed from the bottom of the p-type base region to a further deeper position. The column region located in the outermost periphery and the p-type guard ring region are spaced apart from each other by a distance. A gate electrode lead-out portion electrically coupled to the gate electrode is formed in the p-type guard ring region.