The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
May. 26, 2016
Applicant:
Analog Devices, Inc., Norwood, MA (US);
Inventors:
Shrenik Deliwala, Andover, MA (US);
James Fiorenza, Carlisle, MA (US);
Donghyun Jin, Medford, MA (US);
Assignee:
Analog Devices, Inc., Norwood, MA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/20 (2006.01); H01L 21/02 (2006.01); H01L 21/322 (2006.01); H01L 21/324 (2006.01); H01L 21/205 (2006.01); H01L 21/268 (2006.01); H01L 29/15 (2006.01); H01L 29/205 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 29/155 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02686 (2013.01); H01L 21/3221 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 21/02507 (2013.01); H01L 21/324 (2013.01); H01L 29/7787 (2013.01);
Abstract
A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.