The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Feb. 03, 2016
Jae-yup Chung, Yongin-si, KR;
Jong-shik Yoon, Yongin-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Hee-don Jeong, Hwaseong-si, KR;
Je-min Yoo, Suwon-si, KR;
Kyu-man Cha, Busan, KR;
Jong-mil Youn, Yongin-si, KR;
Hyun-jo Kim, Seoul, KR;
Jae-yup Chung, Yongin-si, KR;
Jong-shik Yoon, Yongin-si, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Hee-don Jeong, Hwaseong-si, KR;
Je-Min Yoo, Suwon-si, KR;
Kyu-man Cha, Busan, KR;
Jong-mil Youn, Yongin-si, KR;
Hyun-jo Kim, Seoul, KR;
Samsung Electronics Co., Ltd., Gyeonggi-Do, KR;
Abstract
An integrated circuit (IC) device includes a fin-type active region formed in a substrate, a step insulation layer on at least one sidewall of the fin-type active region, and a first high-level isolation layer on the at least one sidewall of the fin-type active region. The fin-type active region protrudes from the substrate and extending in a first direction parallel to a main surface of the substrate, includes a channel region having a first conductivity type, and includes the stepped portion. The step insulation layer contacts the stepped portion of the fin-type active region. The step insulation layer is between the first high-level isolation layer and the at least one sidewall of the fin-type active region. The first high-level isolation layer extends in a second direction that is different from the first direction.