The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Sep. 25, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Tae-Hyung Kim, Seoul, KR;

Huichong Shin, Seongnam-Si, KR;

Seokil Kim, Hwaseong-Si, KR;

Young Yun, Yongin-Si, KR;

Jonghyoung Lim, Seoul, KR;

Youkeun Han, Yongin-Si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 29/34 (2006.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01); G11C 11/4093 (2006.01); G11C 11/4076 (2006.01); G11C 5/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/34 (2013.01); G06F 3/0613 (2013.01); G06F 3/0647 (2013.01); G06F 3/0656 (2013.01); G06F 3/0688 (2013.01); G06F 12/1009 (2013.01); G11C 7/109 (2013.01); G11C 7/1045 (2013.01); G06F 2212/1024 (2013.01); G11C 5/04 (2013.01); G11C 11/4076 (2013.01); G11C 11/4093 (2013.01);
Abstract

A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.


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