The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Jan. 28, 2016
Wuhan China Star Optoelectronics Technology Co., Ltd., Wuhan, CN;
WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD., Wuhan, Hubei, CN;
Abstract
The invention provides a GOA circuit for narrow border LCD panel, by disposing a first node leakage prevention unit () comprised of ninth TFT (T), tenth TFT (T) and third capacitor (C), wherein the ninth TFT (T) has gate and source connected to the output clock signal (CK) to form a diode structure to charge the third capacitor (C) and fourth node (H(n)) to high voltage; the tenth TFT (T) clears the fourth node during stage-propagated signal duration to ensure normal charging for the first node (Q(n)). The GOA circuit is applicable to dual-side progressive scanning architecture and also to dual-side interlaced scanning architecture, and able to prevent current leakage in the first node under dual-side interlaced scanning architecture to ensure stable operation of circuit and improve reliability of GOA circuit. Moreover, with only two clock signals on each side, the invention is suitable for narrow border display panel.