The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2018
Filed:
Jan. 11, 2016
International Business Machines Corporation, Armonk, NY (US);
Jesse P. Arroyo, Rochester, MN (US);
Rama K. Hazari, Hyderabad, IN;
Sakethan R. Kotta, Hyderabad, IN;
Kumaraswamy Sripathy, Hyderabad, IN;
International Business Machines Corporation, Armonk, NY (US);
Abstract
A PCI host bridge (PHB) includes a warm reset mode and a full reset mode. When a fatal error occurs, the type of fatal error is determined, a reset mode corresponding to that type of fatal error is determined, and a reset corresponding to the reset mode is performed. A full reset clears the error registers, status registers and configuration registers, which then requires the configuration registers to be reconfigured before the PHB can be reinitialized. A warm reset clears the error registers and status registers, but does not clear the configuration registers. A warm reset thus does not require the time to write to the configuration registers, and the PHB can be reinitialized using the existing configuration data in the configuration registers while link training is done in parallel. When initialization of the PHB after a warm reset is not successful, a full reset is performed.