The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Apr. 25, 2016
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Yoshitsugu Goto, Kawasaki, JP;

Osamu Ishibashi, Kawasaki, JP;

Sadao Miyazaki, Kawasaki, JP;

Jin Abe, Kawasaki, JP;

Masaru Itoh, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 11/10 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0605 (2013.01); G06F 3/0613 (2013.01); G06F 3/0619 (2013.01); G06F 3/0673 (2013.01); G06F 11/1008 (2013.01); G06F 12/0292 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/202 (2013.01); G06F 2212/281 (2013.01); G06F 2212/608 (2013.01); G11C 29/52 (2013.01);
Abstract

A memory apparatus, includes: a memory including memory regions; a table storing a memory address and a number of reading times of data; a first buffer storing first data from another memory apparatus and a first memory address of the first data; a second buffer storing second data to the another memory apparatus and a second memory address of the second data; and a controller configured to store, when a first number of reading times being minimum in the table is smaller than a second number of reading times of the first data, the first data and the first memory address into the first buffer and outputs third data in a memory region of the first number and a third memory address of the third data to the another memory apparatus via the second buffer, and rewrites the third data and memory address with the first data and memory address.


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