The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jun. 02, 2016
Applicant:

Marvell World Trade Ltd., St. Michael, BB;

Inventors:

Tao Zhang, Campbell, CA (US);

Xuemei Liu, Milpitas, CA (US);

Hui Wang, Pleasanton, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/00 (2006.01); H04L 25/40 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01); H03L 7/091 (2006.01); H03K 5/06 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0807 (2013.01); H03K 5/06 (2013.01); H03L 7/0814 (2013.01); H03L 7/091 (2013.01); H04L 7/0037 (2013.01);
Abstract

A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.


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