The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jun. 02, 2017
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Yang-Chuan Chen, Chiayi County, TW;

Chi-Hsueh Wang, Kaohsiung, TW;

Hsiang-Hui Chang, Miaoli County, TW;

Bo-Yu Lin, Taipei, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03K 19/0175 (2006.01); H03F 3/217 (2006.01); H04L 27/34 (2006.01); H04B 1/04 (2006.01); H04W 24/02 (2009.01); H04L 25/02 (2006.01); H04L 25/08 (2006.01); H03M 1/12 (2006.01); G01R 21/06 (2006.01); G01R 23/00 (2006.01); H03F 1/24 (2006.01); H04L 27/20 (2006.01); H03F 1/02 (2006.01); H03F 3/24 (2006.01);
U.S. Cl.
CPC ...
H03K 19/017509 (2013.01); G01R 21/06 (2013.01); G01R 23/00 (2013.01); H03F 1/02 (2013.01); H03F 1/24 (2013.01); H03F 3/2178 (2013.01); H03F 3/24 (2013.01); H03K 19/017581 (2013.01); H03M 1/12 (2013.01); H04B 1/04 (2013.01); H04B 1/0475 (2013.01); H04L 7/0037 (2013.01); H04L 7/0091 (2013.01); H04L 25/028 (2013.01); H04L 25/08 (2013.01); H04L 27/2053 (2013.01); H04L 27/2067 (2013.01); H04L 27/3411 (2013.01); H04L 27/3444 (2013.01); H04W 24/02 (2013.01); H03F 2203/21154 (2013.01); H04B 2001/045 (2013.01); H04B 2001/0408 (2013.01);
Abstract

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.


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