The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

May. 21, 2015
Applicant:

Ams Ag, Unterpremstaetten, AT;

Inventor:

Bernhard Stering, Stainz, AT;

Assignee:

ams AG, Unterpremstaetten, AT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/78 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/561 (2013.01); H01L 21/6836 (2013.01); H01L 23/3114 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A semiconductor substrate () is provided with integrated circuits. Dicing trenches () are formed in the substrate () between the integrated circuits, a polyimide layer () spanning the trenches () is applied above the integrated circuits, a tape layer () is applied above the polyimide layer (), and a layer portion of the substrate () is removed from the substrate side () opposite the tape layer (), until the trenches () are opened and dicing of the substrate () is thus effected. The polyimide layer () is severed in sections () above the trenches () when the tape layer () is removed. The semiconductor chip is provided with a cover layer () laterally confining the polyimide layer () near the trenches (), in particular for forming breaking delimitations ().


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