The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Dec. 14, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Yong Seop Lee, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01); G11C 16/04 (2006.01); G11C 17/14 (2006.01); G11C 17/16 (2006.01); G11C 17/18 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0408 (2013.01); G11C 16/04 (2013.01); G11C 16/0416 (2013.01); G11C 17/14 (2013.01); G11C 17/16 (2013.01); G11C 17/18 (2013.01);
Abstract

A memory cell array includes local blocks disposed in parallel with rows and arrayed along a direction parallel with columns, first selection lines being parallel with the rows and including a couple of first selection lines connected to each of the local blocks, second selection lines disposed in parallel with the columns, and local block selectors disposed between the plurality of local blocks. Each of the local block selectors is disposed between a Qwherein, 'Q' is an odd number local block and a (Q+1)local block among the local blocks to electrically connect unit cells disposed in any one of the Qlocal block and the (Q+1)local block to the second selection lines. The unit cells in the local blocks are disposed at cross points of the first selection lines and the second selection lines, respectively. Each of the unit cells includes a P-channel MOSFET.


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