Transistor plasma charging metal design rule generator

Abstract

A computer-implemented method capable of preparing a design rule indicative of a terminal metal area size of a transistor, minimizing a plasma-induced charging effect to the transistor in a plasma-based process for a dielectric layer performed on a metal layer above the transistor, is provided. The method includes a non-transitory computer readable medium, a design rule generator engine possessing a capability of accurately and swiftly simulating, evaluating and delivering design solutions for interconnect metals and dielectrics while largely saving test chip layout space, and performing the design-for-manufacturing process based on minimized plasma-induced charging effect to the transistor of the integrated circuit design. The disclosed method is applicable to all metal layers in the plasma-based process.