The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jul. 23, 2015
Applicant:

Cavium, Inc., San Jose, CA (US);

Inventors:

Weihuang Wang, Los Gatos, CA (US);

Dan Tu, San Bruno, CA (US);

Guy Hutchison, Santa Clara, CA (US);

Prasanna Vetrivel, San Jose, CA (US);

Assignee:

Cavium, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/00 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); H04L 12/773 (2013.01); H04L 12/721 (2013.01); H04L 12/933 (2013.01); H04L 12/46 (2006.01); H04L 12/701 (2013.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/4282 (2013.01); H04L 12/4625 (2013.01); H04L 45/60 (2013.01); H04L 45/72 (2013.01); H04L 49/109 (2013.01); H04L 45/00 (2013.01);
Abstract

An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.


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